好记心不如烂笔头，为方便以后查看代码及代码重复利用，这里贴出自己写的S3C2440 MMU代码库。使用友善MINI2440开发板，开发环境为RealView MDK 4.22。
该源码结构简单明了，原始工程下载地址：点击打开链接
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Register 0, ID code register：
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unsigned int MMU_ReadID(void)
{
unsigned int id;
__asm(mrc p15, 0, id, c0, c0, 0);
return id;
}
Register 0, cache type register：
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unsigned int MMU_ReadCacheType(void)
{
unsigned int type;
__asm(mrc p15, 0, type, c0, c0, 1);
return type;
}
Register 1, control register：
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void MMU_EnterFastBusMode(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #(3<<30)
mcr p15, 0, r0, c1, c0, 0
}
}
void MMU_EnterSyncMode(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #(1<<31)
orr r0, r0, #(1<<30)
mcr p15, 0, r0, c1, c0, 0
}
}
void MMU_EnterAsyncMode(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #(11<<30)
mcr p15, 0, r0, c1, c0, 0
}
}
void MMU_EnableICache(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #(1<<12)
mcr p15, 0, r0, c1, c0, 0
}
}
void MMU_DisableICache(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #(1<<12)
mcr p15, 0, r0, c1, c0, 0
}
}
void MMU_EnableDCache(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #(1<<2)
mcr p15, 0, r0, c1, c0, 0
}
}
void MMU_DisableDCache(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #(1<<2)
mcr p15, 0, r0, c1, c0, 0
}
}
void MMU_EnableAlignFault(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #(1<<1)
mcr p15, 0, r0, c1, c0, 0
}
}
void MMU_DisableAlignFault(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #(1<<1)
mcr p15, 0, r0, c1, c0, 0
}
}
void MMU_Enable(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #1
mcr p15, 0, r0, c1, c0, 0
}
}
void MMU_Disable(void)
{
unsigned int r0;
__asm{
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #1
mcr p15, 0, r0, c1, c0, 0
}
}
Register 2, translation table base (TTB) register：
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void MMU_SetTTB(void)
{
unsigned int r0 = (unsigned int)TTB;
__asm(mcr p15, 0, r0, c2, c0, 0);
}
Register 3, domain access control register：
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void MMU_SetDomain(unsigned int domain)
{
__asm(mcr p15, 0, domain, c3, c0, 0);
}
Register 7, cache operations register：
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void MMU_InvalidICacheDCache(void)
{
unsigned int r0 = 0;
__asm(mcr p15, 0, r0, c7, c7, 0);
}
void MMU_InvalidICache(void)
{
unsigned int r0 = 0;
__asm(mcr p15, 0, r0, c7, c5, 0);
}
void MMU_InvalidICacheSingleEntry(unsigned int MVA)
{
__asm(mcr p15, 0, MVA, c7, c5, 1);
}
void MMU_PrefechICacheLine(unsigned int MVA)
{
__asm(mcr p15, 0, MVA, c7, c13, 1);
}
void MMU_InvalidDCache(void)
{
unsigned int r0 = 0;
__asm(mcr p15, 0, r0, c7, c6, 0);
}
void MMU_InvalidDCacheSingleEntry(unsigned int MVA)
{
__asm(mcr p15, 0, MVA, c7, c6, 1);
}
void MMU_CleanDCacheSingleEntry(unsigned int MVA)
{
__asm(mcr p15, 0, MVA, c7, c10, 1);
}
void MMU_CleanInvalidDCacheEntry(unsigned int MVA)
{
__asm(mcr p15, 0, MVA, c7, c14, 1);
}
void MMU_CleanDCacheSingleEntry2(unsigned int index)
{
__asm(mcr p15, 0, index, c7, c10, 2);
}
void MMU_CleanInvalidDCacheEntry2(unsigned int index)
{
__asm(mcr p15, 0, index, c7, c14, 2);
}
void MMU_DrainWriteBuffer(void)
{
unsigned int r0 = 0;
__asm(mcr p15, 0, r0, c7, c10, 4);
}
void MMU_WaitForInterrupt(void)
{
unsigned int r0 = 0;
__asm(mcr p15, 0, r0, c7, c0, 4);
}
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Register 8, TLB operations register：
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void MMU_InvalidAllTLB(void)
{
unsigned int r0 = 0;
__asm(mcr p15, 0, r0, c8, c7, 0);
}
void MMU_InvalidITLB(void)
{
unsigned int r0 = 0;
__asm(mcr p15, 0, r0, c8, c5, 0);
}
void MMU_InvalidITLBSingleEntry(unsigned int MVA)
{
__asm(mcr p15, 0, MVA, c8, c5, 1);
}
void MMU_InvalidDTLB(void)
{
unsigned int r0 = 0;
__asm(mcr p15, 0, r0, c8, c6, 0);
}
void MMU_InvalidDTLBSingleEntry(unsigned int MVA)
{
__asm(mcr p15, 0, MVA, c8, c6, 1);
}
Register 9, cache lockdown register：
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unsigned int MMU_ReadDCacheLockdownBase(void)
{
unsigned int r0;
__asm(mrc p15, 0, r0, c9, c0, 0);
r0 >>= 26;
return r0;
}
void MMU_WriteDCacheLockdownBase(unsigned int index)
{
index <<= 26;
__asm(mcr p15, 0, index, c9, c0, 0);
}
unsigned int MMU_ReadICacheLockdownBase(void)
{
unsigned int r0;
__asm(mrc p15, 0, r0, c9, c0, 1);
r0 >>= 26;
return r0;
}
void MMU_WriteICacheLockdownBase(unsigned int index)
{
index <<= 26;
__asm(mcr p15, 0, index, c9, c0, 1);
}
Register 13, FCSE PID register：
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unsigned int MMU_ReadPID(void)
{
unsigned int pid;
__asm(mrc p15, 0, pid, c13, c0, 0);
return (pid >> 25);
}
void MMU_WritePID(unsigned int pid)
{www.2cto.com
pid <<= 25;
__asm(mcr p15, 0, pid, c13, c0, 0);
}
设置Memory Translation Table：
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void MMU_SetMTT(unsigned int vStart, unsigned int vEnd, unsigned int pStart, unsigned int attr)
{
unsigned int vaddr, paddr;
vaddr = vStart;
paddr = pStart;
while(vaddr != (vEnd + 1))
{
TTB[vaddr >> 20] = (paddr & 0xFFF00000) | attr;
vaddr += 0x1000