65 *
66 * Startup Code (reset vector)
67 *
68 * do important init only if we don't start from memory!
69 * relocate armboot to ram
70 * setup stack
71 * jump to second stage
72 *
73 *************************************************************************
74 */
75
76 /*
77 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
78 */
79 _TEXT_BASE:
80 .word TEXT_BASE
81
82 .globl _armboot_start
83 _armboot_start:
84 .word _start
85
86 /*
87 * Note: armboot_end is defined by the (board-dependent) linker script
88 */
89 .globl _armboot_end
90 _armboot_end:
91 .word armboot_end
92
93 // start of snallie
94 .globl _bss_start
95 _bss_start:
96 .word __bss_start
97
98 .globl _bss_end
99 _bss_end:
100 .word armboot_end
101 // end of snallie
/*
* 94~100行 为新加入的代码，定义了2个全局变量，_bss_start和_bss_end，记录未初始化段的起止地址，其中的
* __bss_start和armboot_end 是在连接脚本 board/mini2440/armboot.lds 中定义的，后面309~317行用_bss_start
* 和_bss_end来进行未初始化段数据的初始清零工作。
*/
102
103 /*
104 * _armboot_real_end is the first usable RAM address behind armboot
105 * and the various stacks
106 */
107 .globl _armboot_real_end
108 _armboot_real_end:
109 .word 0x0badc0de
110
111 #ifdef CONFIG_USE_IRQ
112 /* IRQ stack memory (calculated at run-time) */
113 .globl IRQ_STACK_START
114 IRQ_STACK_START:
115 .word 0x0badc0de
116
117 /* IRQ stack memory (calculated at run-time) */
118 .globl FIQ_STACK_START
119 FIQ_STACK_START:
120 .word 0x0badc0de
121 #endif
122
123
124 /*
125 * the actual reset code
126 */
127
128 reset:
129 /*
130 * set the cpu to SVC32 mode
131 */
132 mrs r0,cpsr
133 bic r0,r0,#0x1f
134 orr r0,r0,#0xd3
135 msr cpsr,r0
136
137 /* turn off the watchdog */
138 #if defined(CONFIG_S3C2400)
139 #define pWTCON 0x15300000
140 /* Interupt-Controller base addresses */
141 #define INTMSK 0x14400008
142 /* clock divisor register */
143 #define CLKDIVN 0x14800014
144 #elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) // snallie
/* 144行 S3C2410和S3C2440的Watchdog以及中断屏蔽寄存器的地址相同，所以加入 || defined(CONFIG_S3C2440) 判断 */
145 #define pWTCON 0x53000000
146 /* Interupt-Controller base addresses */
147 #define INTMSK 0x4A000008
148 #define INTSUBMSK 0x4A00001C
149 /* clock divisor register */
150 #define CLKDIVN 0x4C000014
151 #endif
152
153 // snallie
154 #define CLK_CTL_BASE 0x4C000000 /* tekkaman */
155 #define MDIV_405 0x7f << 12 /* tekkaman */
156 #define PSDIV_405 0x21 /* tekkaman */
157 #define MDIV_200 0xa1 << 12 /* tekkaman */
158 #define PSDIV_200 0x31 /* tekkaman */
159 // end of snallie
/* 154~158行引入tekkaman 的几个关于时钟除数因子的定义 */
160
161 ldr r0, =pWTCON
162 mov r1, #0x0
16